The present invention relates to a logic semiconductor integrated circuit (LSI) provided with a central processing unit (CPU) and a digital signal processing unit (DSP) and formed into a semiconductor integrated circuit and an art effectively applied to a data processor (e.g. single-chip microprocessor or single-chip microcomputer) for high-speed processing.
Japanese Patent Application No. 296778/1992 (corresponding to U.S. Pat. No. 08/145157, filed Nov. 3, 1993, now abandoned) is a document describing a single-chip microcomputer in which an arithmetic and logic unit and a multiplier are mounted on the same semiconductor chip.
According to the above invention, a logic LSI chip includes a central processing unit, a bus, a memory, and a multiplier and particularly has a command signal line for transferring a command for a multiplication instruction related to read data from the central processing unit to the multiplier while reading the data out of the memory. As a result, because the command of the multiplication instruction related to read data is transferred from the central processing unit to the multiplier while the central processing unit reads data out of the memory, it is possible to directly transfer data between the memory and the multiplier.
The present inventor and others studied formation of a central processing unit and a digital signal processing unit (DSP) in a semiconductor integrated circuit (LSI) and acceleration of digital signal processing.
The above document realizes acceleration of multiplication by making it possible to directly transfer data from a memory to a multiplier. However, when assuming pipeline processing of instruction execution by a central processing unit, the above document does not consider the situation in which the fetch cycle of an instruction to be executed by a central processing unit competes with the memory access cycle for multiplication.
Moreover, the above document does not consider reading a plurality of operands for addition and multiplication out of a memory in parallel and accelerating operational processing. Furthermore, in this case, it is found by the present inventor and others that the operational easiness of a microcomputer is deteriorated unless considering the relation with external access by the central processing unit.
Furthermore, it is found by the present inventor and others that devising the assignment of codes to a CPU instruction (first instruction) and a DSP instruction (second instruction) and the format of the DSP instruction are also necessary to restrain the increase of the logic scale of an instruction decode circuit to the utmost.
It is an object of the present invention to accelerate digital signal processing by mounting a central processing unit and a digital signal processing unit on one semiconductor integrated circuit.
It is another object of the present invention to restrain the increase of the physical scale of a semiconductor integrated circuit when mounting a central processing unit and a digital signal processing unit on the semiconductor integrated circuit.
It is still another object of the present invention to-provide a data processor whose operational easiness is improved and which includes a central processing unit and a digital processing unit on the same semiconductor chip.
It is still another object of the present invention to provide a data processor in which digital signal processing is accelerated.
It is still another object of the present invention to provide an instruction format (instruction set) preferably applied to a data processor including a central processing unit and a digital signal processing unit in the same semiconductor chip.
It is still another object of the present invention to provide an instruction format (instruction set) capable of restraining the increase of the logic scale of an instruction decode circuit in a data processor including a central processing unit and a digital signal processing unit in the same semiconductor chip.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
A typical embodiment of the invention disclosed in this application is briefly described below.
That is, a semiconductor integrated circuit (microcomputer) comprises a semiconductor chip including:
a central processing unit (2);
first to third address buses (IAB, YAB, and XAB) to which an address is selectively transferred from the central processing unit;
first memories (5 and 7) connected to the first address bus (IAB) and the second address bus (YAB) and to be accessed by an address sent from the central processing unit;
second memories (4 and 6) connected to the first address bus (IAB) and the third address bus (XAB) and to be accessed by an address sent from the central processing unit;
a first data bus (IDB) for transferring data, which is connected to the first and second memories and the central processing unit;
a second data bus (YDB) for transferring data, which is connected to the first memories;
a third data bus (XDB) for transferring data, which is connected to the second memories;
an external interface circuit (12) connected to the first address bus and the first data bus;
a digital signal processing unit (3) connected to the first to third data buses and synchronously operated by the central processing unit; and
a control signal line for transferring a DSP control signal (20) for controlling the operation of the digital signal processing unit from the central processing unit to the digital signal processing unit.
According to the above means, a built-in or an internal memory is divided into the following two types by considering multiply and accumulate operation: first memories (5 and 7) and second memories (4 and 6). Then, the central processing unit (2) is made possible to access the first and second memories by the third internal buses (XAB and XDB) and the second internal buses (YAB and YDB) in parallel. Thereby, it is possible to transfer two data values to the digital signal processing unit from the built-in memory at the same time.
Moreover, because the third internal buses (XAB and XDB) and the second internal buses (YAB and YDB) are also separated from the first internal buses (IAB and IDB) to be interfaced with an external unit, the central processing unit can access an external memory in parallel with the access to the second memories (4 and 6) and the first memories (5 and 7) by using the first internal buses (IAB and IDB).
Thus, because the data processor of the present invention has three internal address buses (IAB, XAB, and YAB) and three internal data buses (IDB, XDB, and YDB) in the first to third internal buses connected to the central processing unit (2), the processor can access different memories at the same clock cycle by using the first to third internal buses. Therefore, even if a program or data is present in an external memory, the data processor of the present invention can easily accelerate arithmetic processing.
To improve the operational easiness of a microcomputer, the first and second memories are preferably are RAM and ROM, respectively.
To accelerate generation of addresses for repetition of the multiply and accumulate operation in the central processing unit, it is preferable to provide a modulo address output portion (200) for the central processing unit. In this case, it is preferable that an address generated by the modulo address output portion can selectively be output to the second or third address bus.
The digital signal processing unit includes first to third data buffer means (MDBI, MDBY, and MDBX) to be individually interfaced with the first to third data buses (IDB, YDB, and XDB), a plurality of register means (305 to 308) being made connectable to each data buffer means through an internal bus, a multiplier (304) and an arithmetic and logic operation unit (302) connected to the internal bus, and a decoder (34) for decoding the DSP control signal and controlling operations of the data buffer means, multiplier, arithmetic and logic operation unit, and register means.
For instruction decoding, a data processor (microcomputer) is formed into a single semiconductor integrated circuit chip including the central processing unit (2), the memories (4 to 7) to be accessed and controlled by the central processing unit, a data bus for transferring data between the memories and the central processing unit, and the digital signal processing unit (3).
An instruction set executable by the microcomputer includes a CPU instruction (first instruction) to be executed by the central processing unit (2) and a DSP instruction to be executed by the digital signal processing unit (3) by making the central processing unit perform some types of processing including address computation for data fetch.
The central processing unit includes an instruction register (25) for fetching a 16-bit fixed-length (first bit length) CPU instruction and a 16-bit or 32-bit (second bit length) DSP instruction through the data bus and a decoder (24) for discriminating the CPU instruction from the DSP instruction in accordance with a plurality of bits of some of the commands fetched by the instruction register and generating a DSP control signal (20) for controlling operations of the digital signal processing unit and a CPU control signal for controlling operations of the central processing unit in accordance with the discrimination result.
For example, a CPU instruction is assigned to a range in which the 4 high-order bits of an instruction code are set to xe2x80x9c0000xe2x80x9d to xe2x80x9c1110xe2x80x9d. A DSP instruction is assigned to a range in which 4 high-order bits of an instruction code are set to xe2x80x9c1111xe2x80x9d. Moreover, 6 high-order bits of an instruction code are used as a xe2x80x9c111100xe2x80x9d instruction code. An instruction in which 6 high-order bits of an instruction code are set to xe2x80x9c111110xe2x80x9d is used as a 32-bit instruction code. However, no instruction is assigned to a range in which 6 high-order bits of an instruction code are set to xe2x80x9c111111xe2x80x9d and the range is used as a vacancy.
Thus, by providing the above rule for assignment of codes to up to 32-bit instructions and thereby decoding a part of each instruction code, that is, 6 high-order bits, it is possible to decide by a decoder with a small logic scale whether the instruction is a CPU instruction, a 16-bit DSP instruction, or a 32-bit DSP instruction. Therefore, it is not necessary to always decode 32 bits at the same time.
The decoder includes a first decode circuit (240) for decoding 6 high-order bits of an instruction register and generating the CPU decode signal (243) and the DSP decode signal (244) and a code converting circuit (242) for outputting a signal obtained by coding 16 low-order bits of an instruction register when discriminating a 32-bit DSP instruction by the first decode circuit and a code representing that the output is invalid when discriminating an instruction other than the 32-bit DSP instruction. The DSP decode signal and the output of the code converting circuit are used as the DSP control signal (20).
When noticing the point of the instruction format of the DSP instruction, a microcomputer is formed into a semiconductor integrated circuit including the central processing unit (2), the digital signal processing unit (3) to be synchronously operated by the central processing unit, and the internal bus (IDB) to which the central processing unit and the digital signal processing unit are connected in common. The central processing unit is provided with execution control means for executing an instruction of a first format having a first code area (bit 9 to bit 0 of the 16-bit DSP instruction shown in FIG. 18) for specifying data transfer to and from the digital signal processing unit for the central processing unit and an instruction of a second format having a second code area (field A of the 32-bit DSP instruction shown in FIGS. 20 and 21) with the same format as the first code area and a third code area (field B of the 32-bit DSP instruction shown in FIGS. 20 and 21) for specifying operational processing using the transferred data specified in-the second code area for the digital signal processing unit.
Thereby, when executing the instruction of the first format and the instruction of the second format respectively, the execution control means can adopt decode means having decode logic common to the first and second code areas, and this contributes to decrease of the logic scale of a microcomputer.
The instruction of the first format and the instruction of the second format have a fourth code area (e.g. bit 15 to bit 10 in a 16-bit DSP instruction or bit 32 to bit 26 in a 32-bit DSP instruction) for indicating tire first format or the second format.
The execution control means includes the instruction register (25) used for the instruction of the first format and the instruction of the second format in common, the decode means (240) for deciding the first and fourth code areas or the second and fourth code areas included in an instruction fetched by the instruction register, and execution means for performing address computation in accordance with the decoded result and performing the data transfer control.
The instruction register is provided with a high-order area (UIR) shared to hold the first and fourth code areas or the second and fourth code areas and a low-order area used to hold the third code area. The decode means includes means (242, 242A, and 242B) for outputting a control signal (248) showing that the instruction register holds the instruction of the second format in accordance with the decoded result of the fourth code area and supplying code data in the third code area from the low-order area to the digital signal processing unit.